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features ? high performance, low power atmel ? avr ? 8-bit microcontroller ? advanced risc architecture ? 131 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20 mips throughput at 20mhz ? on-chip 2-cycle multiplier ? high endurance non-volatile memory segments ? 4/8/16/32kbytes of in-system self-p rogrammable flash program memory ? 256/512/512/1 kbytes eeprom ? 512/1k/1k/2kbytes internal sram ? write/erase cycles: 10,000 flash/100,000 eeprom ? data retention: 20 years at 85 c/100 years at 25 c (1) ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-w rite operation ? programming lock for software security ? atmel ? qtouch ? library support ? capacitive touch button s, sliders and wheels ? qtouch and qmatrix ? acquisition ? up to 64 sense channels ? peripheral features ? two 8-bit timer/counte rs with separate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? six pwm channels ? 8-channel 10-bit adc in tqfp and qfn/mlf package temperature measurement ? 6-channel 10-bit adc in pdip package temperature measurement ? programmable serial usart ? master/slave spi serial interface ? byte-oriented 2-wire se rial interface (philips i 2 c compatible) ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduction, power-save, power-down, standby, and extended standby ? i/o and packages ? 23 programmable i/o lines ? 28-pin pdip, 32-lead tqfp, 28-p ad qfn/mlf and 32-pad qfn/mlf ? operating voltage: ? 1.8 - 5.5v ? temperature range: ?-40 c to 85 c ? speed grade: ? 0 - 4mhz@1.8 - 5.5v, 0 - 10mhz@2.7 - 5.5.v, 0 - 20mhz @ 4.5 - 5.5v ? power consumption at 1mhz, 1.8v, 25 c ? active mode: 0.2ma ? power-down mode: 0.1a ? power-save mode: 0.75a (including 32khz rtc) 8-bit atmel microcontroller with 4/8/16/32k bytes in-system programmable flash atmega48a atmega48pa atmega88a atmega88pa atmega168a atmega168pa atmega328 ATMEGA328P summary rev. 8271ds?avr?05/11
2 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 1. pin configurations figure 1-1. pinout atmega48a/pa/ 88a/pa/168a/pa/328/p 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 gnd vcc gnd vcc (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 pc1 (adc1/pcint9) pc0 (adc0/pcint8) adc7 gnd aref adc6 avcc pb5 (sck/pcint5) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/oc2a/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (txd/pcint17) pd0 (rxd/pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) 32 tqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (pcint14/reset) pc6 (pcint16/rxd) pd0 (pcint17/txd) pd1 (pcint18/int0) pd2 (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 vcc gnd (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) pc1 (adc1/pcint9) pc0 (adc0/pcint8) gnd aref avcc pb5 (sck/pcint5) pb4 (miso/pcint4) pb3 (mosi/oc2a/pcint3) pb2 (ss/oc1b/pcint2) pb1 (oc1a/pcint1) 28 pdip 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 32 mlf top view (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 gnd vcc gnd vcc (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 pc1 (adc1/pcint9) pc0 (adc0/pcint8) adc7 gnd aref adc6 avcc pb5 (sck/pcint5) (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/oc2a/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (txd/pcint17) pd0 (rxd/pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) note: bottom pad should be soldered to ground. 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 28 mlf top view (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 vcc gnd (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/oc2a/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (txd/pcint17) pd0 (rxd/pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) pc1 (adc1/pcint9) pc0 (adc0/pcint8) gnd aref avcc pb5 (sck/pcint5) note: bottom pad should be soldered to ground. table 1-1. 32ufbga - pinout atmega48a/48pa/88a/88pa/168a/168pa 123456 a pd2 pd1 pc6 pc4 pc2 pc1 b pd3 pd4 pd0 pc5 pc3 pc0 c gnd gnd adc7 gnd d vdd vdd aref adc6 e pb6 pd6 pb0 pb2 avdd pb5 f pb7 pd5 pd7 pb1 pb3 pb4
3 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 1.1 pin descriptions 1.1.1 vcc digital supply voltage. 1.1.2 gnd ground. 1.1.3 port b (pb7:0) xtal1/xtal2/tosc1/tosc2 port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. depending on the clock selection fuse settings, pb6 can be used as input to the inverting oscil- lator amplifier and input to the internal clock operating circuit. depending on the clock selection fuse settings, pb7 can be used as output from the inverting oscillator amplifier. if the internal calibrated rc oscillator is us ed as chip clock sour ce, pb7...6 is used as tosc2...1 input for th e asynchronous timer/ counter2 if the as2 bit in assr is set. the various special features of port b are elaborated in ?alternate functions of port b? on page 84 and ?system clock and clock options? on page 27 . 1.1.4 port c (pc5:0) port c is a 7-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the pc5...0 output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. 1.1.5 pc6/reset if the rstdisbl fuse is programmed, pc6 is used as an i/o pin. note that the electrical char- acteristics of pc6 differ from those of the other pins of port c. if the rstdisbl fuse is unprogrammed, pc6 is used as a reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 29-12 on page 324 . shorter pulses are not guaran- teed to generate a reset. the various special features of port c are elaborated in ?alternate functions of port c? on page 87 . 1.1.6 port d (pd7:0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running.
4 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p the various special features of port d are elaborated in ?alternate functions of port d? on page 90 . 1.1.7 av cc av cc is the supply voltage pin for the a/d converter, pc3:0, and adc7:6. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. note that pc6...4 use digital supply voltage, v cc . 1.1.8 aref aref is the analog reference pin for the a/d converter. 1.1.9 adc7:6 (tqfp and qfn/mlf package only) in the tqfp and qfn/mlf package, adc7:6 se rve as analog inputs to the a/d converter. these pins are powered from the analog supply and serve as 10-bit adc channels.
5 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 2. overview the atmega48a/pa/88a/pa/168a/pa/328/p is a low- power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the atmega48a/pa/88a/pa/168a/pa/328/p achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption vers us processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting port c (7) port b (8) port d (8) usart 0 8bit t/c 2 16bit t/c 1 8bit t/c 0 a/d conv. internal bandgap analog comp. spi twi sram flash eeprom watchdog oscillator watchdog timer oscillator circuits / clock generation power supervision por / bod & reset vcc gnd program logic debugwire 2 gnd aref avcc data b u s adc[6..7] pc[0..6] pb[0..7] pd[0..7] 6 reset xtal[1..2] cpu
6 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the atmega48a/pa/88a/pa/168a/pa/328/p provides the following features: 4k/8kbytes of in- system programmable flash with read-while-write capabilities, 256/512/512/1kbytes eeprom, 512/1k/1k/2kbytes sram, 23 general purpose i/o lines, 32 general purpose work- ing registers, three flexible timer/counters with compare modes, internal and external interrupts, a serial programmable usart, a byte -oriented 2-wire serial interface, an spi serial port, a 6-channel 10-bit adc (8 channels in tqfp and qfn/mlf packages), a programmable watchdog timer with internal oscillator, and five software selectable po wer saving modes. the idle mode stops the cp u while allowing the sr am, timer/counters, usart, 2-wire serial inter- face, spi port, and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, dis abling all other chip functions until the next inter- rupt or hardware reset. in power-save mode, th e asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduc- tion mode stops the cpu and all i/o modules exce pt asynchronous timer and adc, to minimize switching noise during adc conversions. in standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. this allows very fast start-up combined with low power consumption. atmel ? offers the qtouch ? library for embedding capacitive touch buttons, sliders and wheels functionality into avr ? microcontrollers. the patented charge -transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop and debug your own touch applications. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot pro- gram running on the avr core. the boot program can use any interface to download the application program in the applic ation flash memory. software in the boot flash section will continue to run while the application flash se ction is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel atmega48a/pa/88a/pa/168a/pa/328/p is a powerful microcontroller that provides a highly flexible and cost effectiv e solution to many embedded control applications. the atmega48a/pa/88a/pa/168a/pa/328/p avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/sim- ulators, in-circuit emulators, and evaluation kits. 2.2 comparison between processors the atmega48a/pa/88a/pa/168a/pa/328/p differ only in memory sizes, boot loader support, and interrupt vector sizes. table 2-1 summarizes the different memory and interrupt vector sizes for the devices. table 2-1. memory size summary device flash eeprom ram interrupt vector size atmega48a 4kbytes 256bytes 512bytes 1 instruction word/vector atmega48pa 4kbytes 256bytes 512bytes 1 instruction word/vector atmega88a 8kbytes 512bytes 1kbytes 1 instruction word/vector
7 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p atmega48a/pa/88a/pa/168a/pa/328/p support a real read-while-write self-programming mechanism. there is a separate boot loader section, and the spm instruction can only execute from there. in atmega 48a/48pa there is no read-while-write support and no separate boot loader section. the spm instruction can execute from the entire flash. atmega88pa 8kbytes 512bytes 1kbytes 1 instruction word/vector atmega168a 16kbytes 512bytes 1kbyt es 2 instruction words/vector atmega168pa 16kbytes 512bytes 1kbyt es 2 instruction words/vector atmega328 32kbytes 1kbytes 2kbytes 2 instruction words/vector ATMEGA328P 32kbytes 1kbytes 2kbytes 2 instruction words/vector table 2-1. memory size summary (continued) device flash eeprom ram interrupt vector size
8 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 3. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr. note: 1. 4. data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 5. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructio ns that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 6. capacitive touch sensing the atmel ? qtouch ? library provides a simple to use so lution to realize touch sensitive inter- faces on most atmel avr ? microcontrollers. the qtouch library includes support for the atmel qtouch and atmel qmatrix ? acquisition methods. touch sensing can be added to any application by linking the appropriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the touch chan- nels and sensors, and then calling the touch sens ing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: www.atmel.com/qtouchlibrary . for implementation details and other information, refer to the atmel qtouch library user guide - also available for down load from atmel website.
9 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 7. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? (0xf8) reserved ? ? ? ? ? ? ? ? (0xf7) reserved ? ? ? ? ? ? ? ? (0xf6) reserved ? ? ? ? ? ? ? ? (0xf5) reserved ? ? ? ? ? ? ? ? (0xf4) reserved ? ? ? ? ? ? ? ? (0xf3) reserved ? ? ? ? ? ? ? ? (0xf2) reserved ? ? ? ? ? ? ? ? (0xf1) reserved ? ? ? ? ? ? ? ? (0xf0) reserved ? ? ? ? ? ? ? ? (0xef) reserved ? ? ? ? ? ? ? ? (0xee) reserved ? ? ? ? ? ? ? ? (0xed) reserved ? ? ? ? ? ? ? ? (0xec) reserved ? ? ? ? ? ? ? ? (0xeb) reserved ? ? ? ? ? ? ? ? (0xea) reserved ? ? ? ? ? ? ? ? (0xe9) reserved ? ? ? ? ? ? ? ? (0xe8) reserved ? ? ? ? ? ? ? ? (0xe7) reserved ? ? ? ? ? ? ? ? (0xe6) reserved ? ? ? ? ? ? ? ? (0xe5) reserved ? ? ? ? ? ? ? ? (0xe4) reserved ? ? ? ? ? ? ? ? (0xe3) reserved ? ? ? ? ? ? ? ? (0xe2) reserved ? ? ? ? ? ? ? ? (0xe1) reserved ? ? ? ? ? ? ? ? (0xe0) reserved ? ? ? ? ? ? ? ? (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) reserved ? ? ? ? ? ? ? ? (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) reserved ? ? ? ? ? ? ? ? (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) reserved ? ? ? ? ? ? ? ? (0xd3) reserved ? ? ? ? ? ? ? ? (0xd2) reserved ? ? ? ? ? ? ? ? (0xd1) reserved ? ? ? ? ? ? ? ? (0xd0) reserved ? ? ? ? ? ? ? ? (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) reserved ? ? ? ? ? ? ? ? (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) udr0 usart i/o data register 201 (0xc5) ubrr0h usart baud rate register high 205 (0xc4) ubrr0l usart baud rate register low 205 (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) ucsr0c umsel01 umsel00 upm01 upm00 usbs0 ucsz01 /udord0 ucsz00 / ucpha0 ucpol0 203/214 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 202 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 201
10 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) reserved ? ? ? ? ? ? ? ? (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 ?246 (0xbc) twcr twint twea twsta twsto twwc twen ?twie 243 (0xbb) twdr 2-wire serial interface data register 245 (0xba) twar twa6 twa5 twa4 tw a3 twa2 twa1 twa0 twgce 246 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 ?twps1twps0 245 (0xb8) twbr 2-wire serial interface bit rate register 243 (0xb7) reserved ? ? ? ? ? ? ? (0xb6) assr ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub 166 (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) ocr2b timer/counter2 output compare register b 164 (0xb3) ocr2a timer/counter2 output compare register a 164 (0xb2) tcnt2 timer/counter2 (8-bit) 164 (0xb1) tccr2b foc2a foc2b ? ? wgm22 cs22 cs21 cs20 163 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 ? ?wgm21wgm20 160 (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) ocr1bh timer/counter1 - output compare register b high byte 140 (0x8a) ocr1bl timer/counter1 - outp ut compare register b low byte 140 (0x89) ocr1ah timer/counter1 - output compare register a high byte 140 (0x88) ocr1al timer/counter1 - output compare register a low byte 140 (0x87) icr1h timer/counter1 - input capture register high byte 140 (0x86) icr1l timer/counter1 - input capture register low byte 140 (0x85) tcnt1h timer/counter1 - counter register high byte 140 (0x84) tcnt1l timer/counter1 - counter register low byte 140 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ?139 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 138 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 136 (0x7f) didr1 ? ? ? ? ? ?ain1dain0d 251 (0x7e) didr0 ? ? adc5d adc4d adc3d adc2d adc1d adc0d 268 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
11 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) admux refs1 refs0 adlar ? mux3 mux2 mux1 mux0 264 (0x7b) adcsrb ?acme ? ? ? adts2 adts1 adts0 267 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 265 (0x79) adch adc data register high byte 267 (0x78) adcl adc data register low byte 267 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) timsk2 ? ? ? ? ? ocie2b ocie2a toie2 165 (0x6f) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 141 (0x6e) timsk0 ? ? ? ? ? ocie0b ocie0a toie0 113 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 76 (0x6c) pcmsk1 ? pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 76 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pc int4 pcint3 pcint2 pcint1 pcint0 76 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra ? ? ? ?isc11isc10isc01isc00 73 (0x68) pcicr ? ? ? ? ? pcie2 pcie1 pcie0 (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal oscillator calibration register 38 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr prtwi prtim2 prtim0 ? prtim1 prspi prusart0 pradc 43 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 38 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 56 0x3f (0x5f) sreg i t h s v n z c 10 0x3e (0x5e) sph ? ? ? ? ? (sp10) 5. sp9 sp8 13 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 13 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie (rwwsb) 5. ? (rwwsre) 5. blbset pgwrt pgers selfprgen 295 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr ?bods (6) bodse (6) pud ? ? ivsel ivce 46/70/94 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf 56 0x33 (0x53) smcr ? ? ? ?sm2sm1sm0se 41 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) reserved ? ? ? ? ? ? ? ? 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 249 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 177 0x2d (0x4d) spsr spif wcol ? ? ? ? ? spi2x 176 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 175 0x2b (0x4b) gpior2 general purpose i/o register 2 26 0x2a (0x4a) gpior1 general purpose i/o register 1 26 0x29 (0x49) reserved ? ? ? ? ? ? ? ? 0x28 (0x48) ocr0b timer/counter0 output compare register b 0x27 (0x47) ocr0a timer/counter0 output compare register a 0x26 (0x46) tcnt0 timer/counter0 (8-bit) 0x25 (0x45) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 0x23 (0x43) gtccr tsm ? ? ? ? ? psrasy psrsync 145/167 0x22 (0x42) eearh (eeprom address register high byte) 5. 22 0x21 (0x41) eearl eeprom address register low byte 22 0x20 (0x40) eedr eeprom data register 22 0x1f (0x3f) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 22 0x1e (0x3e) gpior0 general purpose i/o register 0 26 0x1d (0x3d) eimsk ? ? ? ? ? ?int1int0 74 0x1c (0x3c) eifr ? ? ? ? ? ? intf1 intf0 74 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
12 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on regi sters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instruct ions, 0x20 must be added to these addresses. the atmega48a/pa/88a/pa/168a/pa/328/p is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and ou t instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for atmega88a/88pa/168a/168pa/328/328p. 6. bods and bodse only available for picopower devices atmega48pa/88pa/168pa/328p 0x1b (0x3b) pcifr ? ? ? ? ? pcif2 pcif1 pcif0 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) tifr2 ? ? ? ? ? ocf2b ocf2a tov2 165 0x16 (0x36) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 141 0x15 (0x35) tifr0 ? ? ? ? ? ocf0b ocf0a tov0 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) reserved ? ? ? ? ? ? ? ? 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) reserved ? ? ? ? ? ? ? ? 0x0d (0x2d) reserved ? ? ? ? ? ? ? ? 0x0c (0x2c) reserved ? ? ? ? ? ? ? ? 0x0b (0x2b) portd portd7 portd6 portd 5 portd4 portd3 portd2 portd1 portd0 95 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 95 0x09 (0x29) pind pind7 pind6 pi nd5 pind4 pind3 pind2 pind1 pind0 95 0x08 (0x28) portc ? portc6 portc5 portc4 portc3 portc2 portc1 portc0 94 0x07 (0x27) ddrc ? ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 94 0x06 (0x26) pinc ? pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 94 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 94 0x04 (0x24) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 94 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 94 0x02 (0x22) reserved ? ? ? ? ? ? ? ? 0x01 (0x21) reserved ? ? ? ? ? ? ? ? 0x0 (0x20) reserved ? ? ? ? ? ? ? ? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
13 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 8. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp (1) k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call (1) k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2
14 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0...6 z,c,n,v 1 swap rd swap nibbles rd(3...0) rd(7...4),rd(7...4) rd(3...0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 mnemonics operands description operation flags #clocks
15 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p note: 1. these instructions are only available in atmega168pa and ATMEGA328P. pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
16 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 9. ordering information 9.1 atmega48a note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see ?speed grades? on page 322 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) power supply (v) ordering code (2) package (1) operational range 20 (3) 1.8 - 5.5 atmega48a-au atmega48a-aur (5) atmega48a-ccu atmega48a-ccur (5) atmega48a-mmh (4) atmega48a-mmhr (4)(5) atmega48a-mu atmega48a-mur (5) atmega48a-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) package type 32a 32-lead, thin (1.0 mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6 mm package, ball pitch 0.5 mm , ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45 mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50 mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip)
17 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 9.2 atmega48pa note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. 3. see ?speed grades? on page 322 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply ordering code (2) package (1) operational range 20 1.8 - 5.5 atmega48pa-au atmega48pa-aur (5) atmega48pa-ccu atmega48pa-ccur (5) atmega48pa-mmh (4) atmega48pa-mmhr (4)(5) atmega48pa-mu atmega48pa-mur (5) atmega48pa-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) atmega48pa-an atmega48pa-anr (4) atmega48pa-mmn atmega48pa-mmnr (4) atmega48pa-mn atmega48pa-mnr (4) atmega48pa-pn 32a 32a 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 105 c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip)
18 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 9.3 atmega88a note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see ?speed grades? on page 322 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) power supply (v) ordering code (2) package (1) operational range 20 (3) 1.8 - 5.5 atmega88a-au atmega88a-aur (5) atmega88a-ccu atmega88a-ccur (5) atmega88a-mmh (4) atmega88a-mmhr (4)(5) atmega88a-mu atmega88a-mur (5) atmega88a-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip)
19 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 9.4 atmega88pa note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see ?speed grades? on page 322 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply (v) ordering code (2) package (1) operational range 20 1.8 - 5.5 atmega88pa-au atmega88pa-aur (5) atmega88pa-ccu atmega88pa-ccur (5) atmega88pa-mmh (4) atmega88pa-mmhr (4)(5) atmega88pa-mu atmega88pa-mur (5) atmega88pa-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) atmega88pa-an atmega88pa-anr (5) atmega88pa-mmn atmega88pa-mmnr (5) atmega88pa-mn atmega88pa-mnr (5) atmega88pa-pn 32a 32a 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 105 c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5 mm, ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45 mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50 mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip)
20 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 9.5 atmega168a note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see ?speed grades? on page 322 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply (v) ordering code (2) package (1) operational range 20 1.8 - 5.5 atmega168a-au atmega168a-aur (5) atmega168a-ccu atmega168a-ccur (5) atmega168a-mmh (4) atmega168a-mmhr (4)(5) atmega168a-mu atmega168a-mur (5) atmega168a-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6 mm package, ball pitch 0.5mm, ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip)
21 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 9.6 atmega168pa note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see ?speed grades? on page 322 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply (v) ordering code (2) package (1) operational range 20 1.8 - 5.5 atmega168pa-au atmega168pa-aur (5) atmega168pa-ccu atmega168pa-ccur (5) atmega168pa-mmh (4) atmega168pa-mmhr (4)(5) atmega168pa-mu atmega168pa-mur (5) atmega168pa-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) 20 1.8 - 5.5 atmega168pa-an atmega168pa-anr (5) atmega168pa-mn atmega168pa-mnr (5) atmega168pa-pn 32a 32a 32m1-a 32m1-a 28p3 industrial (-40 c to 105 c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip)
22 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 9.7 atmega328 note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see figure 29-1 on page 322 . 4. nipdau lead finish. 5. tape & reel speed (mhz) power supply (v) ordering code (2) package (1) operational range 20 (3) 1.8 - 5.5 atmega328-au atmega328-aur (5) atmega328-mmh (4) atmega328-mmhr (4)(5) atmega328-mu atmega328-mur (5) atmega328-pu 32a 32a 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf)
23 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 9.8 ATMEGA328P note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see figure 29-1 on page 322 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply (v) ordering code (2) package (1) operational range 20 1.8 - 5.5 ATMEGA328P-au ATMEGA328P-aur (5) ATMEGA328P-mmh (4) ATMEGA328P-mmhr (4)(5) ATMEGA328P-mu ATMEGA328P-mur (5) ATMEGA328P-pu 32a 32a 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) ATMEGA328P-an ATMEGA328P-anr (5) ATMEGA328P-mn ATMEGA328P-mnr (5) ATMEGA328P-pn 32a 32a 32m1-a 32m1-a 28p3 industrial (-40 c to 105 c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf)
24 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 10. packaging information 10.1 32a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 3 2a, 32-lead, 7 x 7 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) c 32a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b notes: 1. this package conforms to jedec reference ms-026, variation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ common dimen s ion s (unit of measure = mm) s ymbol min nom max note
25 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 10.2 32cc1 title drawing no. gpc rev. packa g e drawin g contact: packagedra w ings@atmel.com b cag 3 2cc1 , 32- b all (6 x 6 array), 4 x 4 x 0.6 mm package, b all pitch 0.50 mm, ultra thin, fine-pitch ball grid array (ufbga) 32cc1 a ? ? 0.60 a1 0.12 ? ? a2 0.3 8 ref b 0.25 0.30 0.35 1 b 1 0.25 ? ? 2 d 3.90 4.00 4.10 d1 2.50 bsc e 3.90 4.00 4.10 e1 2.50 bsc e 0.50 bsc 07/06/10 b 1 common dimen s ion s (unit of meas u re = mm) 123456 b a c d e f e d e 32-? b e d b a pin#1 id 0.0 8 a1 a d1 e1 a2 a1 ball cor n er 123456 f c s ide view bottom view top view s ymbol min nom max note n ote1: dimension ?b? is measured at the maximum ball dia. in a plane parallel to the seating plane. n ote2: dimension ? b 1? is the soldera b le s u rface defined b y the opening of the solder resist layer. e
26 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 10.3 28m1 title drawing no. gpc rev. packa g e drawin g contact: packagedra w ings@atmel.com 2 8 m1 zb v b 2 8 m1, 28-pad, 4 x 4 x 1.0 mm body, lead pitch 0.45 mm, 2.4 x 2.4 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 10/24/0 8 s ide view pin 1 id bottom view top view n ote: the terminal #1 id is a laser-marked feat u re . d e e k a1 c a d2 e2 y l 1 2 3 b 1 2 3 0.45 common dimen s ion s (unit of meas u re = mm) s ymbol min nom max note a 0. 8 0 0.90 1.00 a1 0.00 0.02 0.05 b 0.17 0.22 0.27 c 0.20 ref d 3.95 4.00 4.05 d2 2.35 2.40 2.45 e 3.95 4.00 4.05 e2 2.35 2.40 2.45 e 0.45 l 0.35 0.40 0.45 y 0.00 ? 0.0 8 k 0.20 ? ? r 0.20 0.4 ref (4x)
27 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 10.4 32m1-a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 3 2m1-a , 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm, e 32m1-a 5/25/06 3.10 mm exposed pad, micro lead frame package (mlf) common dimen s ion s (unit of measure = mm) s ymbol min nom max note d1 d e1 e e b a3 a2 a1 a d2 e2 0.08 c l 1 2 3 p p 0 1 2 3 a 0.80 0.90 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a3 0.20 ref b 0.18 0.23 0.30 d d1 d2 2.95 3.10 3.25 4.90 5.00 5.10 4.70 4.75 4.80 4.70 4.75 4.80 4.90 5.00 5.10 e e1 e2 2.95 3.10 3.25 e 0.50 bsc l 0.30 0.40 0.50 p ? ? 0.60 ? ? 12 o note: jedec standard mo-220, fig. 2 (anvil singulation), vhhd-2. top view s ide view bottom view 0 pin 1 id pin #1 notch (0.20 r) k 0.20 ? ? k k
28 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 10.5 28p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28p3 , 28-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 28p3 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb b2 (4 places) common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.5724 a1 0.508 ? ? d 34.544 ? 34.798 note 1 e 7.620 ? 8.255 e1 7.112 ? 7.493 note 1 b 0.381 ? 0.533 b1 1.143 ? 1.397 b2 0.762 ? 1.143 l 3.175 ? 3.429 c 0.203 ? 0.356 eb ? ? 10.160 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
29 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 11. errata 11.1 errata atmega48a the revision letter in this section refers to the revision of the atmega48a device. 11.1.1 rev. d ? analog mux can be turned off when setting acme bit 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 11.2 errata atmega48pa the revision letter in this section refers to the revision of the atmega48pa device. 11.2.1 rev. d ? analog mux can be turned off when setting acme bit 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 11.3 errata atmega88a the revision letter in this section refers to the revision of the atmega88a device. 11.3.1 rev. f ? analog mux can be turned off when setting acme bit 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit.
30 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 11.4 errata atmega88pa the revision letter in this section refers to the revision of the atmega88pa device. 11.4.1 rev. f ? analog mux can be turned off when setting acme bit 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 11.5 errata atmega168a the revision letter in this section refers to the revision of the atmega168a device. 11.5.1 rev. e ? analog mux can be turned off when setting acme bit 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 11.6 errata atmega168pa the revision letter in this section refers to the revision of the atmega168pa device. 11.6.1 rev e ? analog mux can be turned off when setting acme bit 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit.
31 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 11.7 errata atmega328 the revision letter in this section refers to the revision of the atmega328 device. 11.7.1 rev d ? analog mux can be turned off when setting acme bit 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 11.7.2 rev c not sampled. 11.7.3 rev b ? analog mux can be turned off when setting acme bit ? unstable 32khz oscillator 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. unstable 32khz oscillator the 32khz oscillator does not work as system clock. the 32khz oscillator used as asyn- chronous timer is inaccurate. problem fix/ workaround none. 11.7.4 rev a ? analog mux can be turned off when setting acme bit ? unstable 32khz oscillator 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. unstable 32khz oscillator the 32khz oscillator does not work as system clock. the 32khz oscillator used as asyn- chronous timer is inaccurate. problem fix/ workaround none.
32 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 11.8 errata ATMEGA328P the revision letter in this section refers to the revision of the ATMEGA328P device. 11.8.1 rev d ? analog mux can be turned off when setting acme bit 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 11.8.2 rev c not sampled. 11.8.3 rev b ? analog mux can be turned off when setting acme bit ? unstable 32khz oscillator 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer en abled) bit in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. unstable 32khz oscillator the 32khz oscillator does not work as system clock. the 32khz oscillator used as asyn- chronous timer is inaccurate. problem fix/ workaround none. 11.8.4 rev a ? unstable 32khz oscillator 1. unstable 32khz oscillator the 32khz oscillator does not work as system clock. the 32khz oscillator used as asyn- chronous timer is inaccurate. problem fix/ workaround none.
33 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 12. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 12.1 rev. 8271d ? 05/11 12.2 rev. 8271c ? 08/10 12.3 rev. 8271b ? 04/10 1. added atmel qtouch sensing capablity feature 2. updated ?register description? on page 94 with pinxn as r/w. 3. added a footnote to the pinxn, page 94 . 4. updated 5. updated ?ordering information? , ?atmega328? on page 546 . added ?atmega328- mmh? and ?atmega328-mmhr?. 6. updated ?ordering information? , ?ATMEGA328P? on page 547 . added ?ATMEGA328P- mmh? and ?ATMEGA328P-mmhr?. 7. added ?ordering information? for atmega48pa/88pa/168pa/328p @ 105 c 8. updated ?errata atmega328? on page 555 and ?errata ATMEGA328P? on page 556 98. updated the datasheet according to the atmel new brand style guide. 1. added 32ufbga pinout, table 1-1 on page 2 . 2. updated the ?sram data memory? , figure 8-3 on page 19 . 3. updated ?ordering information? on page 540 with ccu and ccur code related to ?32cc1? package drawing. 4. ?32cc1? package drawing added on ?packaging information? on page 548 . 1. updated table 9-8 with correct value for time r oscilliator at xtal2/tos2 2. corrected use of sbis instructions in assembly code examples. 3. corrected bod and bodse bits to r/w in section 10.11.2 on page 46 , section 12.5 on page 70 and section 14.4 on page 94 4. figures for bandgap characterization added, figure 30-34 on page 350 , figure 30-81 on page 375 , figure 30-128 on page 400 , figure 30-175 on page 425 , figure 30-222 on page 450 , figure 30-269 on page 475 , figure 30-316 on page 500 and figure 30- 363 on page 525 . 5. updated ?packaging information? on page 548 by replacing 28m1 with a correct cor- responding package.
34 8271ds?avr?05/11 atmega48a/pa/88a/pa/168a/pa/328/p 12.4 rev. 8271a ? 12/09 1. new datasheet 8271 with merged information for atmega48pa, atmega88pa, atmega168pa and atmega48a, atmega88a andatmega168a. also included information on atmega328 and ATMEGA328P 2 changes done: ? new devices added: atmega48a/atmega88a/atmega168a and atmega328 ? updated feature description ? updated table 2-1 on page 6 ? added note for bod disable on page 41 . ? added note on bod and bodse in ?mcucr ? mcu control register? on page 94 and ?register description? on page 295 ? added limitation informat in for the application ?boot loader support ? read-while-write self-programming? on page 280 ? added limitiation information for ?program and data memory lock bits? on page 297 ? added specified dc characteristics ? added typical characteristics ? removed exception information in ?address match unit? on page 224 .
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